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| 128Mx64 bits Unbuffered DDR SO-DIMM HYMD512M646A(L)FS8-D43/D4 Document Title 128Mx64 bits Unbuffered DDR SO-DIMM Revision History No. 0.1 0.2 Initial Draft 1) Reflected a "notational" change in module thickness on page 14 - Not Real ! 2) Corrected some typos History Draft Date Dec. 2003 Apr. 2004 Remark This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / Apr. 2004 1 128Mx64 bits Unbuffered DDR SO-DIMM HYMD512M646A(L)FS8-D43/D4 DESCRIPTION Hynix HYMD512M646A(L)FS8-D43/D4 series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline Dual In-Line Memory Modules (SO-DIMMs) which are organized as 128Mx64 high-speed memory arrays. Hynix HYMD512M646A(L)FS8-D43/D4 series consists of eight 128Mx8 DDR MCP SDRAM in FBGA packages on a 200pin glass-epoxy substrate. Hynix HYMD512M646A(L)FS8-D43/D4 series provide a high performance 8-byte interface in 67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition. Hynix HYMD512M646A(L)FS8-D43/D4 series is designed for high speed of up to 200MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. Hynix HYMD512M646A(L)FS8-D43/D4 series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer. FEATURES * * * * * * 1GB (128M x 64) Unbuffered DDR SO-DIMM based on 128Mx8 DDR MCP SDRAM 200-pin small outline dual in-line memory module (SO-DIMM) 2.6V +/- 0.1V VDD and VDDQ Power supply All inputs and outputs are compatible with SSTL_2 interface Fully differential clock operations (CK & /CK) with 200MHz All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Data(DQ), Data strobes and Write masks latched on both rising and falling edges of the clock * * * * * * * * Data inputs on DQS centers when write (centered DQ) Data strobes synchronized with output data for read and input data for write Programmable CAS Latency 3 supported Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode tRAS Lock-out function supported Internal four bank operations with single pulsed RAS Auto refresh and self refresh supported 8192 refresh cycles / 64ms * ORDERING INFORMATION Part No. HYMD512M646A(L)FS8-D43 HYMD512M646A(L)FS8-D4 Power Supply VDD=2.6V VDDQ=2.6V Clock Frequency 200MHz (DDR400 3-3-3) 200MHz (DDR400 3-4-4) Interface SSTL_2 Form Factor 200pin Unbuffered SO-DIMM 67.6mm x 31.75mm x 1mm * JEDEC Defined Specifications compliant This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / Apr. 2004 2 HYMD512M646A(L)FS8-D43/D4 PIN DESCRIPTION Pin CK0, /CK0, CK1, /CK1 CS0, CS1 CKE0, CKE1 /RAS, /CAS, /WE A0 ~ A12 BA0, BA1 DQ0~DQ63 DQS0~DQS7 DM0~DM7 VDD Pin Description Differential Clock Inputs Chip Select Input Clock Enable Input Commend Sets Inputs Address Bank Address Data Inputs/Outputs Data Strobe Inputs/Outputs Data-in Mask Power Supply Pin VDDQ VSS VREF VDDSPD SA0~SA2 SCL SDA VDDID DU NC Pin Description DQs Power Supply Ground Reference Power Supply Power Supply for SPD E2PROM Address Inputs E2PROM Clock E2PROM Data I/O VDD Identification Flag Do not Use No Connection PIN ASSIGNMENT Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Name VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS DQ16 DQ17 VDD DQS2 DQ18 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Name VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22 Pin 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 Name VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD NC NC VSS NC NC VDD NC DU VSS NC NC VDD CKE1 NC A12 Pin 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 Name VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD NC NC VSS NC NC VDD NC DU VSS VSS VDD VDD CKE0 DU A11 Pin 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 Name A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 /WE /CS0 NC VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS Pin 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 Name A8 VSS A6 A4 A2 A0 VDD BA1 /RAS /CAS /CS1 DU VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS Pin 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 Name DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD VDDID Pin 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 Name DQ46 DQ47 VDD /CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU Rev. 0.2 / Apr. 2004 3 HYMD512M646A(L)FS8-D43/D4 FUNCTIONAL BLOCK DIAGRAM CKE1 CKE0 /CS1 /CS0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS /CS0 /CS1 /CKE0 /CKE1 DQS4 DM4 DQ32 DQ33 DQ34 DM I/O0 I/O1 I/O2 DQS /CS0 /CS1 /CKE0 /CKE1 D0 DQ35 DQ36 DQ37 DQ38 DQ39 I/O3 I/O4 I/O5 I/O6 I/O7 D4 DQS1 DM1 DQ8 DQ9 DM I/O0 I/O1 I/O2 DQS /CS0 /CS1 /CKE0 /CKE1 DQS5 DM5 DQ40 DQ41 DQ42 DM I/O0 I/O1 I/O2 DQS /CS0 /CS1 /CKE0 /CKE1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O3 I/O4 I/O5 I/O6 I/O7 D1 DQ43 DQ44 DQ45 DQ46 DQ47 I/O3 I/O4 I/O5 I/O6 I/O7 D5 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM DQS /CS0 /CS1 /CKE0 /CKE1 I/O0 I/O1 I/O2 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O0 I/O1 I/O2 DQS /CS0 /CS1 /CKE0 /CKE1 I/O3 I/O4 I/O5 I/O6 I/O7 D2 I/O3 I/O4 I/O5 I/O6 I/O7 D6 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O0 I/O1 I/O2 DQS /CS0 /CS1 /CKE0 /CKE1 DQS7 DM7 DQ56 DQ57 DQ58 DM I/O0 I/O1 I/O2 DQS /CS0 /CS1 /CKE0 /CKE1 I/O3 I/O4 I/O5 I/O6 I/O7 D3 DQ59 DQ60 DQ61 DQ62 DQ63 I/O3 I/O4 I/O5 I/O6 I/O7 Serial PD D7 VDD SPD VDD /VDDQ SPD DO-D15 DO-D15 DO-D15 Strap:see Note 4 SCL SDA WP A0 A1 SA1 A2 SA2 VREF VSS VDDID SA0 Note : BA0BA1 A0A12 /RAS /CAS /WE BA0-BA1 : SDRAMs D0-D7 A0-A12 : SDRAMs D0-D7 /RAS : SDRAMs D0-D7 /CAS : SDRAMs D0-D7 /WE : SDRAMs D0-D7 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors : 22 Ohms ? 5%. 4. VDDID strap connections (for memory device VDD, VDDQ) : STRAP OUT (OPEN) : VDD = VDDQ STRAP IN (VSS) : VDD ? VDDQ Rev. 0.2 / Apr. 2004 4 HYMD512M646A(L)FS8-D43/D4 ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature (Ambient) Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Output Short Circuit Current Power Dissipation Soldering Temperature Time TA TSTG VIN, VOUT VDD VDDQ IOS PD TSOLDER Symbol 0 ~ 70 -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0.5 ~ 3.6 50 1.0 x # of Components 260 / 10 Rating o Unit C oC V V V mA W oC / Sec Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITIONS (TA= 0 to 70 oC, Voltage referenced to VSS= 0V) Parameter Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage Termination Voltage Reference Voltage Symbol VDD VDDQ VIH VIL VTT VREF Min 2.5 2.5 VREF + 0.15 -0.3 VREF - 0.04 0.49*VDDQ Typ. 2.6 2.6 VREF 0.5*VDDQ Max 2.7 2.7 VDDQ + 0.3 VREF - 0.15 VREF + 0.04 0.51*VDDQ Unit V V V V V V 3 2 1 Note Note : 1. VDDQ must not exceed the level of VDD. 2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration. 3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same. Peak to peak noise on VREF may not exceed +/- 2% of the DC value. AC OPERATING CONDITIONS (TA= 0 to 70 oC, Voltage referenced to VSS= 0V) Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 VREF - 0.31 VDDQ + 0.6 0.5*VDDQ+0.2 Max Unit V V V V 1 2 Note Note : 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. Rev. 0.2 / Apr. 2004 5 HYMD512M646A(L)FS8-D43/D4 AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Reference Voltage Termination Voltage AC Input High Level Voltage (VIH, min) AC Input Low Level Voltage (VIL, max) Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input Signal maximum peak swing Input minimum Signal Slew Rate Termination Resistor (RT) Series Resistor (RS) Output Load Capacitance for Access Time Measurement (CL) Value VDDQ x 0.5 VDDQ x 0.5 VREF + 0.31 VREF - 0.31 VREF VTT 1.5 1 50 25 30 Unit V V V V V V V V/ns pF Rev. 0.2 / Apr. 2004 6 HYMD512M646A(L)FS8-D43/D4 CAPACITANCE (TA=25oC, f=100MHz ) Parameter Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Data Input / Output Capacitance A0 ~ A13, BA0, BA1 /RAS, /CAS, /WE CKE0, CKE1 /CS0, /CS1 CK0, /CK0, CK1, /CK1 DM0 ~ DM7 DQ0 ~ DQ63, DQS0 ~ DQS7 Pin Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIO1 Min TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD TBD Unit pF pF pF pF pF pF pF Note : 1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT VTT RT=50 Output Zo=50 VREF CL=30pF Rev. 0.2 / Apr. 2004 7 HYMD512M646A(L)FS8-D43/D4 DC CHARACTERISTICS I (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Input Leakage Current Add, CMD, /CS, CKE Symbol Min. -32 Max 32 Unit Note ILI CK0, /CK0, CK1, /CK1 uA -16 16 5 VTT - 0.76 uA V V -5 VTT + 0.76 - 1 2 IOH = -15.2mA IOL = +15.2mA Output Leakage Current Output High Voltage Output Low Voltage Note : ILO VOH VOL 1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 2.7V Rev. 0.2 / Apr. 2004 8 HYMD512M646A(L)FS8-D43/D4 DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Symbol Test Condition One bank; Active - Precharge ; tRC=tRC(min); tCK=tCK(min) ; DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle One bank; Active - Read - Precharge; Burst Length=2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle All banks idle; Power down mode; CKE=Low, tCK=tCK(min) /CS=High, All banks idle; tCK=tCK(min); CKE=High; address and control inputs changing once per clock cycle. VIN=VREF for DQ, DQS and DM /CS>=Vih(min); All banks idle; CKE>=Vih(min); Addresses and other control inputs stable, Vin=Vref for DQ, DQS and DM One bank active; Power down mode; CKE=Low, tCK=tCK(min) /CS=HIGH; CKE=HIGH; One bank; Active-Precharge; tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); IOUT=0mA Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle tRC=tRFC(min) - 14*tCK for DDR400 at 200Mhz CKE =< 0.2V; External clock on; tCK=tCK(min) Normal Low Power Speed -D43 1480 -D4 Unit Note Operating Current IDD0 mA Operating Current Precharge Power Down Standby Current IDD1 1880 mA IDD2P 160 mA Idle Standby Current IDD2F 560 mA Idle Quiet Standby Current Active Power Down Standby Current IDD2Q 520 mA IDD3P 192 mA Active Standby Current IDD3N 680 mA Operating Current IDD4R 2520 mA Operating Current IDD4W 2520 Auto Refresh Current Self Refresh Current Operating Current Four Bank Operation IDD5 IDD6 IDD7 2680 80 40 4600 mA mA mA Four bank interleaving with BL=4, Refer to the following page for detailed test condition Rev. 0.2 / Apr. 2004 9 HYMD512M646A(L)FS8-D43/D4 AC CHARACTERISTICS (AC operating conditions unless otherwise noted) DDR400 (D43) Parameter Symbol Min Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Active to Read with Auto Precharge Delay Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time Write Recovery Time Internal Write to Read Command Delay Auto Precharge Write Recovery + Precharge Time System Clock Cycle Time Clock High Level Width Clock Low Level Width Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew DQS-Out edge to Data-Out edge Skew Data-Out hold time from DQS CL = 3 tRC tRFC tRAS tRAP tRCD tRRD tCCD tRP tWR tWTR tDAL tCK tCH tCL tAC tDQSCK tDQSQ tQH 55 70 40 tRCD or tRASmin DDR400 (D4) Unit Note Max 70K 10 0.55 0.55 0.7 0.55 0.4 - Min 60 70 40 tRCD or tRASmin Max 70K 10 0.55 0.55 0.7 0.55 0.4 ns ns ns ns ns ns CK ns ns CK CK ns CK CK ns ns ns ns 1,10 15 16 15 10 1 15 15 2 (tWR/tCK) + (tRP/tCK) 18 10 1 18 15 2 (tWR/tCK) + (tRP/tCK) 5 0.45 0.45 -0.7 -0.55 tHP -tQHS min (tCL,tCH) - 5 0.45 0.45 -0.7 -0.55 tHP -tQHS min (tCL,tCH) - Clock Half Period Data Hold Skew Factor Data-out high-impedance window from CK,/CK Data-out low-impedance window from CK, /CK Input Setup Time (fast slew rate) Input Hold Time (fast slew rate) Input Setup Time (slow slew rate) Input Hold Time (slow slew rate) tHP tQHS tHZ tLZ tIS tIH tIS tIH 0.5 tAC(Max) 0.5 tAC(Max) ns ns ns 1,9 10 17 -0.7 0.6 0.6 0.7 0.7 0.7 -0.7 0.6 0.6 0.7 0.7 0.7 ns ns 2,3,5,6 ns ns 2,4,5,6 ns Rev. 0.2 / Apr. 2004 10 HYMD512M646A(L)FS8-D43/D4 AC CHARACTERISTICS (AC operating conditions unless otherwise noted) DDR400 (D43) Parameter Symbol Min Input Pulse Width Write DQS High Level Width Write DQS Low Level Width Clock to First Rising edge of DQS-In DQS falling edge to CK setup time DQS falling edge hold time from CK Data-In Setup Time to DQS-In (DQ & DM) Data-in Hold Time to DQS-In (DQ & DM) DQ & DM Input Pulse Width Read DQS Preamble Time Read DQS Postamble Time Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit Self Refresh to Any Execute Command Average Periodic Refresh Interval Note : 1. 2. 3. 4. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE. For command/address input slew rate >=1.0V/ns For command/address input slew rate >=0.5V/ns and <1.0V/ns This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns. Input Setup / Hold Slew-rate Derating Table. Input Setup / Hold Slew-rate V/ns 0.5 0.4 0.3 6. 7. CK, /CK slew rates are >=1.0V/ns These parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by design or tester correlation. 11 Delta tIS ps 0 +50 +100 Delta tIH ps 0 0 0 tIPW tDQSH tDQSL tDQSS tDSS tDSH tDS tDH tDIPW tRPRE tRPST tWPRES tWPREH tWPST tMRD tXSC tREFI 2.2 0.35 0.35 0.72 0.2 0.2 0.4 0.4 1.75 0.9 0.4 0 0.25 0.4 2 200 1.1 0.6 0.6 7.8 Max 1.28 Min 2.2 0.35 0.35 0.72 0.2 0.2 0.4 0.4 1.75 0.9 0.4 0 0.25 0.4 2 200 1.1 0.6 0.6 7.8 Max 1.28 ns CK CK CK CK CK ns ns ns CK CK CK CK CK CK CK us 8 6,7,11 , 12,13 6 6 DDR400 (D4) Unit Note - continued - 5. Rev. 0.2 / Apr. 2004 HYMD512M646A(L)FS8-D43/D4 8. 9. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to n-channel variation of the output drivers. This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns. Input Setup / Hold Slew-rate Derating Table. Input Setup / Hold Slew-rate V/ns 0.5 0.4 0.3 Delta tDS ps 0 +75 +150 Delta tDH ps 0 +75 +150 10. 11. 12. 13. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF +/-310mV for a duration of up to 2ns. I/O Input Level mV +280 Delta tDS ps +50 Delta tDH ps +50 14. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1=0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V. (1/SlewRate1)-(1/SlewRate2) ns/V 0 +/-0.25 +/- 0.5 Delta tDS ps 0 +50 +100 Delta tDH ps 0 +50 +100 15. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotonic. tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. Example: For DDR266B at CL=2.5 and tCK = 7.5 ns, tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67) Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clock For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be tRAS - BL/2 x tCK. tHZ and tLZ transitions occur in the same access time windows as valid data trasitions. These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ). 16. 17. 18. Rev. 0.2 / Apr. 2004 12 HYMD512M646A(L)FS8-D43/D4 SIMPLIFIED COMMAND TRUTH TABLE Command Extended Mode Register Set Mode Register Set Device Deselect H No Operation Bank Active Read H Read with Autoprecharge Write H Write with Autoprecharge Precharge All Banks H Precharge selected Bank Read Burst Stop Auto Refresh Entry Self Refresh Exit L H L H Precharge Power Down Mode Entry H L L H Exit L H L Active Power Down Mode (Clock Suspend) H Entry Exit H L L L H V X V V X 1 1 H X H X H X 1 1 H X H X H X X 1 1 H X H X H X 1 H H H X H L L L L H H L L X H L L X L H H X X 1 X L L H L X L X X V 1 1 1 1 X L H L L CA H H X X L H L H CA H L V 1,4 1,5 H X X L L H L H H H H RA L V 1,3 1 V 1 1 CKEn-1 H H CKEn X X /CS L L H /RAS L L X /CAS L L X /WE L L X X 1 ADDR A10/ AP OP code OP code BA Note 1,2 1,2 ( H=Logic High Level, L=Logic Low Level, X=Don't Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note : 1. LDM/UDM states are Don't Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory compoment in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time (tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. Rev. 0.2 / Apr. 2004 13 HYMD512M646A(L)FS8-D43/D4 PACKAGE DIMENSIONS 2.00 mm Front 2.00 mm Component Keepout Area 31.75 mm 20.00 mm 1 39 41 199 Back 67.60 mm Side 1.1mm Max z 3.8mm Max Rev. 0.2 / Apr. 2004 14 SERIAL PRESENCE DETECT SPD SPECIFICATION (128Mx64 Unbuffered DDR SO-DIMM) Rev. 0.2 / Apr. 2004 15 HYMD512M646A(L)FS8-D43/D4 SERIAL PRESENCE DETECT Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function Description Number of Bytes written into serial memory at module manufacturer Total number of Bytes in SPD device Fundamental memory type Number of row address on this assembly Number of column address on this assembly Number of physical banks on DIMM Module data width Module data width (continued) Module voltage Interface levels(VDDQ) DDR SDRAM cycle time at CAS Latency=X (tCK) DDR SDRAM access time from clock at CL=X (tAC) Module configuration type Refresh rate and type Primary DDR SDRAM width Error checking DDR SDRAM data width Minimum clock delay for back-to-back random column address(tCCD) Burst lengths supported Number of banks on each DDR SDRAM CAS latency supported CS latency WE latency DDR SDRAM module attributes DDR SDRAM device attributes : General Bin Sort :D43(DDR400 3-3-3) / D4(DDR400 3-4-4) Function Supported D43 128 Bytes 256 Bytes DDR SDRAM 13 11 2Bank 64 Bits SSTL 2.5V 5.0ns +/-0.7ns None 7.8us & Self refresh x8 N/A 1 CLK 2,4,8 4 Banks 2, 2.5, 3 0 1 +/-0.2Voltage tolerance, Concurrent Auto Precharge tRAS Lock Out 6.0ns +/-0.7ns 7.5ns +/-0.75ns 15ns 10ns 15ns 40ns 512MB 0.60ns 0.60ns 0.40ns 0.40ns Undefined 55ns 70ns 10ns 0.4ns 0.5ns Undefined Initial release - Hexa Value D43 80h 08h 07h 0Dh 0Bh 02h 40h 00h 04h 50h 70h 00h 82h 08h 00h 01h 0Eh 04h 1Ch 01h 02h 20h D4 128 Bytes 256 Bytes DDR SDRAM 13 11 2Bank 64 Bits SSTL 2.5V 5.0ns +/-0.7ns None 7.8us & Self refresh x8 N/A 1 CLK 2,4,8 4 Banks 2, 2.5, 3 0 1 +/-0.2Voltage tolerance, Concurrent Auto Precharge tRAS Lock Out 6.0ns +/-0.7ns 7.5ns +/-0.75ns 18ns 10ns 18ns 40ns 512MB 0.60ns 0.60ns 0.40ns 0.40ns Undefined 58ns 70ns 10ns 0.4ns 0.5ns Undefined Initial release - D4 80h 08h 07h 0Dh 0Bh 02h 40h 00h 04h 50h 70h 00h 82h 08h 00h 01h 0Eh 04h 1Ch 01h 02h 20h Note 1 1 2 2 Differential Clock Input Differential Clock Input C0h C0h 23 24 25 26 27 28 29 30 31 32 33 34 35 41 42 43 44 45 62 63 DDR SDRAM cycle time at CL=X-0.5(tCK) DDR SDRAM access time from clock at CL=X-0.5(tAC) DDR SDRAM cycle time at CL=X-1(tCK) DDR SDRAM access time from clock at CL=X-1(tAC) Minimum row precharge time(tRP) Minimum row activate to row active delay(tRRD) Minimum RAS to CAS delay(tRCD) Minimum active to precharge time(tRAS) Module row density Command and address signal input setup time(tIS) Command and address signal input hold time(tIH) Data signal input setup time(tDS) Data signal input hold time(tDH) Minimum active / auto-refresh time ( tRC) Minimum auto-refresh to active/auto-refresh command period(tRFC) Maximum cycle time (tCK max) Maximim DQS-DQ skew time(tDQSQ) Maximum read data hold skew factor(tQHS) SPD Revision code Checksum for Bytes 0~62 60h 70h 75h 75h 3Ch 28h 3Ch 28h 80h 60h 60h 40h 40h 00h 37h 46h 28h 28h 50h 00h 00h A8h 60h 70h 75h 75h 48h 28h 48h 28h 80h 60h 60h 40h 40h 00h 3Ah 46h 28h 28h 50h 00h 00h C3h 2 2 2 2 36~40 Reserved for VCSDRAM 46~61 Superset information(may be used in future) Rev. 0.2 / Apr. 2004 16 HYMD512M646A(L)FS8-D43/D4 SERIAL PRESENCE DETECT Byte# 64 65~71 Function Description Manufacturer JEDEC ID Code --------- Manufacturer JEDEC ID Code - continued Function Supported D43 Hynix JEDEC ID - Hexa Value D43 ADh 00h 0*h 1*h 2*h 3*h 4*h 5*h 48h 59h 4Dh 44h 35h 31h 32h 4Dh 36h 34h 36h 41h 46h 38h 2Dh 44h 34h 33h D4 Hynix JEDEC ID - D4 ADh 00h 0*h 1*h 2*h 3*h 4*h 5*h 48h 59h 4Dh 44h 35h 31h 32h 4Dh 36h 34h 36h 41h 46h 38h 2Dh 44h 34h - Note 72 Manufacturing location Hynix(Korea Area) Hynix(Korea Area) HSA(United States Area) HSA(United States Area) HSE(Europe Area) HSE(Europe Area) HSJ(Japan Area) HSJ(Japan Area) Singapore Singapore Asia Area Asia Area H Y M D 5 1 2 M 6 4 6(8K refresh,4Bank) A F 8 `-' D 4 3 H Y M D 5 1 2 M 6 4 6(8K refresh,4Bank) A F 8 `-' D 4 - 6 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 Manufacture part number(Hynix Memory Module) -------- Manufacture part number(Hynix Memory Module) -------- Manufacture part number(Hynix Memory Module) Manufacture part number (DDR SDRAM) Manufacture part number(Memory density) Manufacture part number(Module Depth) ------- Manufacture part number(Module Depth) Manufacture part number(Module type) Manufacture part number(Data width) -------Manufacture part number(Data width) Manufacture part number(Refresh, # of Bank.) Manufacture part number(Component Generation) Manufacture part number(Component configuration) Manufacture part number(Module type) Manufacture part number(Hyphen) Manufacture part number(Minimum cycle time) Manufacture part number(Minimum cycle time) Manufacture revision code(Minimum cycle time) Manufacture revision code(for Component) Manufacture revision code (for PCB) Manufacturing date(Year) Manufacturing date(Week) Module serial number 3 3 4 Undefined Undefined Undefined Undefined 00h 00h 00h 00h 5 5 99~127 Manufacturer specific data (may be used in future) 128~255 Open for customer use Note : 1. The bank address is excluded 2. These value is based on the component specification 3. These bytes are programmed by code of date week & date year 4. These bytes apply to Hynix's own Module Serial Number system 5. These bytes undefined and coded as `00h' 6. Refer to Hynix web site Rev. 0.2 / Apr. 2004 17 |
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